Fetching from the wire…
01
02
03
04
05
06
07
08
Public story · 2026-08-25 · high
The chip packs 432GB of HBM4 per GPU and a 72-GPU rack that moves 1.7 petabytes a second.
Why now: Hot Chips 2026 is where AMD chose to make the MI400 numbers public, ahead of any shipping hardware.
AMD detailed the MI400 at Hot Chips 2026: 40.26 petaflops of MXFP4 compute and 432GB of HBM4 per GPU, per ServeTheHome's writeup.
The MI400's peak MXFP4 throughput is four times the MI355X's, and per-GPU memory jumps from 288GB of HBM3E to 432GB of HBM4. More memory per GPU means fewer chips can hold a given model, which lowers hardware costs for teams building inference clusters.
At MXFP6 and MXFP8 the chip runs 20.13 petaflops each. It also holds 315 teraflops of vector FP16 and matrix FP32 for workloads that need full precision. Memory bandwidth per GPU is 23.3 TB/s.
Eight accelerator complex dies sit on TSMC's N2 process, with fabric, cache, and I/O split onto separate N3P dies. The chip totals 256 work group processors and 192MB of global L2 cache.
AMD's own benchmark claim centers on inference: 20 TB/s of measured MLA decode bandwidth in FP8. The company says that's 3.8x the MI355X's throughput at about 2.4x the energy efficiency. Decode bandwidth determines how fast a model streams tokens to a user, so this number matters more for inference workloads than the petaflops figure.
A 72-GPU Helios rack moves 1.7 PB/s. ServeTheHome's report doesn't say when MI400 systems ship or what they'll cost.
Each link below shares sources, entities, or timing with this story.
AMD unveiled its first rack-scale system to directly contest Nvidia at the rack level, with engineering samples in H2 2026 and mass production targeted Q2 2027. Microsoft joins Meta, OpenAI and Oracle as customers; Meta plans 1 gigawatt of Helios racks by year-end against a lo...
The Chips and Cheese teardown details eight Accelerator Complex Dies on TSMC N2 plus two I/O dies and two fabric-and-cache dies on N3, twelve HBM4 stacks on 2048-bit buses, 192 channels, 256 Work Group Processors at 2.4GHz for up to 40.26 PFLOPS of OCP MXFP4. The Helios rack p...
The August 23 Hot Chips session walked HBM1 through HBM4, with HBM3E's 128 banks per die doubling to 256 in HBM4, and showed a typical GPU package exceeding 12,000 square millimeters once eight HBM4 stacks are included. Roughly 3x as much silicon is consumed to deliver the sam...
PR #19378 landed in llama.cpp this week, and I think most people are underselling what it means. Backend-agnostic tensor parallelism via --split-mode tensor makes multi-GPU inference work across AMD, Intel, and Apple Silicon. Not just CUDA. Everything. For context: llama.cpp h...
TrendForce reporting via Tom's Hardware says prototype variants run 192GB or 256GB, down from the announced 288GB, with some configs using fewer than 16 stacks and substituting HBM4 for HBM4E. Driver is tightening HBM supply across SK hynix, Samsung, and Micron. At GTC 2025 co...
Reuters, via Tech Startups, reports capital released against deployment milestones with Anthropic deploying up to two gigawatts of Instinct MI450 starting 2027. Same structure as Nvidia/OpenAI: compute vendor capital flowing to the lab that commits to buy the silicon. A two-gi...
MindPattern daily
One email a day at 7 AM. Sources and a take on every story. Unsubscribe anytime.