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Infra2026-08-28 · source-backed
HBM Design Architecture Fellow Raghu Sreeramaneni said HBM needs roughly three times DDR5's wafer area for the same capacity, and when asked whether newer generations close the gap, said it definitely would not get better (Tom's Hardware). An HBM4 die runs 256 memory banks against DDR5's 32. HBM will consume 23% of total DRAM wafer output in 2026, up from about 19%, which is the mechanism behind every consumer memory price story this year.
Each link below shares sources, entities, or timing with this story.
Reports surfacing August 7 say Samsung, SK Hynix and Micron have sold their entire 2027 allocation for both DRAM and HBM. Consumer impact is already visible: 32GB DDR5 kits are well over $400 versus roughly $100 in September 2025, a 4x move after DRAM contract prices jumped 50...
Internal survey data shows 81.5% of foundry staff and nearly 50% of the broader semiconductor division intending to leave within two years. The cause is bonus structure tied to division P&L: SK Hynix paid roughly $476,000 per employee, Samsung's memory division ~$400,000, and...
TrendForce reporting via Tom's Hardware says prototype variants run 192GB or 256GB, down from the announced 288GB, with some configs using fewer than 16 stacks and substituting HBM4 for HBM4E. Driver is tightening HBM supply across SK hynix, Samsung, and Micron. At GTC 2025 co...
The August 23 Hot Chips session walked HBM1 through HBM4, with HBM3E's 128 banks per die doubling to 256 in HBM4, and showed a typical GPU package exceeding 12,000 square millimeters once eight HBM4 stacks are included. Roughly 3x as much silicon is consumed to deliver the sam...
SemiAnalysis CEO details how long-context inference's KV Cache has exploded HBM demand, with memory requiring 4x the wafer area of DDR. NVIDIA locked up TSMC N3 allocation early — explaining why H100 pricing is higher today than three years ago despite more supply. Source
NVIDIA is building a new inference processor integrating Groq's Language Processing Unit technology (acquired December 2025). The chip uses on-chip SRAM instead of HBM, delivering up to 80 TB/s memory bandwidth (~10x H100). OpenAI committed to 3 GW of dedicated inference capac...
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